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The Opportunity Every board Lumai builds has to run multi-gigabit links and feed high-current ASIC and FPGA rails. Getting those right before the board is fabricated is the difference between a working system and a respin cycle. This role owns the modelling, the stackups, the materials and the design rules that make it work, and has a direct say in the decisions that prevent the respin. The Role You will own signal and power integrity across our boards and packages. That means pre-layout channel studies that set routing topologies, stackups, materials and constraints; post-layout analysis of critical channels, including insertion and return loss, crosstalk, and eye and COM analysis with IBIS-AMI models; optimisation of vias, breakouts, connector launches and the transitions into our optical engines; and PDN impedance targets, decoupling strategies and DC drop analysis for high-current rails. What is genuinely hard is that the channels cross boundaries - chip, package, interposer, board and optical engine - and a model is only as good as its weakest corner. You will spend as much time at the bench as in the tool, correlating what you predicted against what the hardware does, and feeding that back into design rules. By month six, you will have signed off the critical channels on at least one board, built the model libraries and design guidelines the team reuses, and be the person whose analysis decides when a layout is ready to release. What You'll Do Run pre-layout channel studies to set routing topologies, stackups, materials and design constraints for high-speed interfaces. Carry out post-layout SI analysis of critical channels: insertion and return loss, crosstalk, and eye and COM analysis using IBIS-AMI models. Design and optimise vias, breakouts, connector launches, and the transitions into optical engines and co-packaged components. Set PDN impedance targets, design decoupling strategies, and run DC drop and AC PDN analysis for high-current ASIC and FPGA rails. Support package, interposer and board co-simulation with the ASIC team to keep channel and power integrity sound end to end. Correlate simulation with lab measurements using TDRs, VNAs and oscilloscopes, and feed the results back into models and design rules. Evaluate and characterise PCB materials, connectors and cable assemblies with suppliers and fabricators. Build up our SI/PI methodology, model libraries and design guidelines so they can be reused across projects. What We're Looking For Must-have A degree in electronic engineering, physics or a related discipline, plus proven SI/PI experience on high-speed PCB and/or package designs. Proficiency with at least one major EM and circuit simulation suite, such as Ansys HFSS/SIwave, Keysight ADS or Cadence Sigrity/Clarity. Strong understanding of transmission line theory, S-parameters, crosstalk, loss mechanisms and channel compliance metrics such as eye diagrams and COM. Experience with IBIS and IBIS-AMI models for SerDes and memory interface simulation. Solid knowledge of PDN design, including impedance targeting, decoupling optimisation and DC IR drop analysis. Strong preference for Hands-on measurement with VNAs, TDRs and high-speed oscilloscopes, and the ability to correlate measurements with simulation. 56G/112G PAM4 channels, or PCIe Gen5/6 compliance. Package and interposer co-simulation, including chip-package-board analysis. Low-loss PCB materials and fabrication tolerances and their effect on high-speed performance. Scripting (Python, MATLAB) to automate simulation and post-processing. About Lumai Lumai is the optical compute company building the next generation of AI infrastructure. Spun out of optics research at the University of Oxford in 2021, we compute with light instead of electrons.

Senior HW Engineer – Signal and Power Integrity

No apliques sin prepararte

Senior HW Engineer – Signal and Power Integrity

No apliques sin prepararte