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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix team is building custom AI compute cores, RISC-V CPUs, and chiplet-based architectures for datacenter, edge, and automotive AI. Design Verification Engineers on this team validate compute IP and subsystems and build scalable DV infrastructure to keep verification fast, automated, and production-grade. This role is hybrid, based out of Toronto, ON, Austin, TX or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are • Experienced in modern verification methodologies with strong SystemVerilog skills and exposure to structured testbench development. • Comfortable working from block-level to system-level verification and reasoning about microarchitecture behavior from specs and waveforms. • Proficient in Linux environments with Python, or Bash scripting for automate builds, parse logs, manage CI pipelines. • Skilled in coverage-driven verification and confident debugging across RTL, testbench, and workload scenarios. • Motivated by AI hardware and eager to learn verification strategies for new architectures and domains. What We Need • Contribute to verification of Tensix IP and subsystems from early planning through tape-out, owning coverage goals and driving them to closure. • Build and maintain reusable verification environments, agents, scoreboards, and supporting infrastructure in SystemVerilog and Python. • Develop constrained-random and directed tests and close functional, code, and assertion coverage using data-driven approaches. • Debug complex issues across RTL and testbench while collaborating with design, firmware, compiler, and architecture teams. • Help evolve DV infrastructure including regression flows, CI/CD integration, EDA compute environments, and reproducible setups. • Nice to have: Exposure to functional safety (FuSa) verification concepts for automotive AI workloads. • Nice to have: Familiarity with formal verification methodologies, SVA (SystemVerilog Assertions), or formal property verification for complex control logic and microarchitectural corner cases. What You Will Learn • How Tenstorrent verifies AI-native compute architectures including Tensix cores, RISC-V CPUs, matrix units, vector units, and datapath. • How simulation, emulation, and software-driven workloads combine to validate both functional correctness and performance. • How numerical precision formats such as BF16, FP4, and INT8 and on-chip dataflow impact verification complexity and coverage strategy. • How to build scalable DV infrastructure across hybrid compute environments including contain

Staff Design Verification Engineer, AI HW

Don't apply unprepared

Staff Design Verification Engineer, AI HW

Don't apply unprepared